1 of 8 102999 features 10 years minimum data retention in the absence of external power data is automatically protected during power loss unlimited write cycles low-power cmos operation read and write access times as fast as 70 ns lithium energy source is electrically disconnected to retain freshness until power is applied for the first time full 10% v cc operating range (ds1265y) optional 5% v cc operating range (ds1265ab) optional industrial temperature range of -40 c to +85 c, designated ind pin assignment pin description a0 - a19 - address inputs dq0 - dq7 - data in/data out ce - chip enable we - write enable oe - output enable v cc - power (+5v) gnd - ground nc - no connect description the ds1265 8m nonvolatile srams are 8,388,608-bit, fully static nonvolatile srams organized as 1,048,576 words by 8 bits. each nv sram has a self-contained lithium energy source and control circuitry which constantly monitors v cc for an out-of-tolerance condition. when such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. there is no limit on the number of write cycles which can be executed and no additional support circuitry is required for microprocessor interfacing. ds1265y/ab 8m nonvolatile sram www.dalsemi.com 13 1 2 3 4 5 6 7 8 9 10 11 12 14 35 36-pin encapsulated package 740-mil extended a18 a14 a7 a6 a5 a4 a3 a2 a0 a1 v cc a 19 nc a 15 a 17 we a 13 a 8 a 9 a 11 oe a 10 dq7 ce 36 34 33 32 31 30 29 28 27 26 25 23 24 nc a16 a12 nc dq0 dq1 15 16 22 21 dq6 dq5 17 18 gnd dq2 dq3 dq4 19 20
ds1265y/ab 2 of 8 102999 read mode the ds1265 devices execute a read cycle whenever we (write enable) is inactive (high) and ce (chip enable) and oe (output enable) are active (low). the unique address specified by the 20 address inputs (a 0 - a 19 ) defines which of the 1,048,576 bytes of data is accessed. valid data will be available to the eight data output drivers within t acc (access time) after the last address input signal is stable, providing that ce and oe (output enable) access times are also satisfied. if oe and ce access times are not satisfied, then data access must be measured from the later-occurring signal ( ce or oe ) and the limiting parameter is either t co for ce or t oe for oe rather than t acc . write mode the ds1265 devices execute a write cycle whenever we and ce signals are active (low) after address inputs are stable. the later-occurring falling edge of ce or we will determine the start of the write cycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe control signal should be kept inactive (high) during write cycles to avoid bus contention. however, if the output drivers are enabled ( ce and oe active) then we will disable the outputs in t odw from its falling edge. data retention mode the ds1265ab provides full functional capability for v cc greater than 4.75 volts and write protects by 4.5 volts. the ds1265y provides full functional capability for v cc greater than 4.5 volts and write protects by 4.25 volts. data is maintained in the absence of v cc without any additional support circuitry. the nonvolatile static rams constantly monitor v cc . should the supply voltage decay, the nv srams automatically write protect themselves, all inputs become don?t care, and all outputs become high- impedance. as v cc falls below approximately 3.0 volts, a power switching circuit connects the lithium energy source to ram to retain data. during power-up, when v cc rises above approximately 3.0 volts, the power switching circuit connects external v cc to ram and disconnects the lithium energy source. normal ram operation can resume after v cc exceeds 4.75 volts for the ds1265ab and 4.5 volts for the ds1265y. freshness seal each ds1265 device is shipped from dallas semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than v tp , the lithium energy source is enabled for battery backup operation.
ds1265y/ab 3 of 8 102999 absolute maximum ratings* voltage on any pin relative to ground -0.3v to +7.0v operating temperature 0c to 70c; -40c to +85c for ind parts storage temperature -40c to +70c; -40c to +85c for ind parts soldering temperature 260c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (t a : see note 10) parameter symbol min typ max units notes ds1265ab power supply voltage v cc 4.75 5.0 5.25 v ds1265y power supply voltage v cc 4.5 5.0 5.5 v logic 1 input voltage v ih 2.2 v cc v logic 0 input voltage v il 0 +0.8 v dc electrical (v cc =5v = 5% for ds1265ab) characteristics (t a : see note 10) (v cc =5v = 10% for ds1265y) parameter symbol min typ max units notes input leakage current i il -2.0 +2.0 a i/o leakage current i io -2.0 +2.0 a output current @ 2.4v i oh -1.0 ma output current @ 0.4v i ol 2.0 ma standby current ce =2.2v i ccs1 1.0 1.5 ma standby current ce =v cc -0.5v i ccs2 100 250 a operating current i cco1 85 ma write protection voltage (ds1265ab) v tp 4.50 4.62 4.75 v write protection voltage (ds1265y) v tp 4.25 4.37 4.5 v capacitance (t a =25 c) parameter symbol min typ max units notes input capacitance c in 10 20 pf output capacitance c i/o 10 20 pf
ds1265y/ab 4 of 8 102999 ac electrical (v cc =5v = 5% for ds1265ab) characteristics (t a : see note 10) (v cc =5v = 10% for ds1265y) ds1265ab-70 ds1265y-70 ds1265ab-100 ds1265y-100 parameter symbol min max min max units notes read cycle time t rc 70 100 ns access time t acc 70 100 ns oe to output valid t oe 35 50 ns ce to output valid t co 70 100 ns oe or ce to output active t coe 5 5 ns 5 output high z from deselection t od 25 35 ns 5 output hold from address change t oh 55 ns write cycle time t wc 70 100 ns write pulse width t wp 55 75 ns 3 address setup time t aw 00 ns write recovery time t wr1 t wr2 5 15 5 15 ns ns 12 13 output high z from we t odw 25 35 ns 5 output active from we t oew 5 5 ns 5 data setup time t ds 30 40 ns 4 data hold time t dh1 t dh2 0 10 0 10 ns ns 12 13 timing diagram: read cycle see note 1
ds1265y/ab 5 of 8 102999 timing diagram: write cycle 1 timing diagram: write cycle 2 see notes 2, 3, 4, 6, 7, 8 and 13
ds1265y/ab 6 of 8 102999 power-down/power-up condition see note 11 power-down/power-up timing (t a : see note 10) parameter symbol min typ max units notes v cc fail detect to ce and we inactive t pd 1.5 s 11 v cc slew from v tp to 0v t f 150 s v cc slew from 0v to v tp t r 150 s v cc valid to ce and we inactive t pu 2ms v cc valid to end of write protection t rec 125 ms (t a =25 c) parameter symbol min typ max units notes expected data retention time t dr 10 years 9 warning: under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode. notes: 1. we is high for a read cycle. 2. oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high-impedance state. 3. t wp is specified as the logical and of ce or we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t ds is measured from the earlier of ce or we going high. 5. these parameters are sampled with a 5 pf load and are not 100% tested. 6. if the ce low transition occurs simultaneously with or latter than the we low transition, the output buffers remain in a high-impedance state during this period. 7. if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in high-impedance state during this period.
ds1265y/ab 7 of 8 102999 8. if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high-impedance state during this period. 9. each ds1249 has a built-in switch that disconnects the lithium source until v cc is first applied by the user. the expected t dr is defined as accumulative time in the absence of v cc starting from the time power is first applied by the user. 10. all ac and dc electrical characteristics are valid over the full operating temperature range. for commercial products, this range is 0 c to 70 c. for industrial products (ind), this range is -40 c to +85 c. 11. in a power-down condition the voltage on any pin may not exceed the voltage on v cc . 12. t wr1 and t dh1 are measured from we going high. 13. t wr2 and t dh2 are measured from ce going high. dc test conditions ac test conditions outputs open output load: 100 pf + 1ttl gate all voltages are referenced to ground input pulse levels: 0v to 3.0v timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5 ns ordering information ds1265 ttp - sss - iii operating temperature range blank: 0 to 70 ind: -40 to +85 c access speed 70: 70 ns 100: 100 ns package type blank: 36-pin 600-mil dip v cc tolerance ab: 5% y: 10%
ds1265y/ab 8 of 8 102999 ds1265y/ab nonvolatile sram 36-pin 740-mil extended module, long pkg 36-pin dim min max a in. mm 2.080 52.83 2.100 53.34 b in. mm 0.720 18.29 0.740 18.80 c in. mm 0.355 9.02 0.405 10.29 d in. mm 0.180 4.57 0.210 5.33 e in. mm 0.015 0.38 0.025 0.63 f in. mm 0.120 3.05 0.150 4.06 g in. mm 0.090 2.29 0.110 2.79 h in. mm 0.590 14.99 0.630 16.00 j in. mm 0.008 0.20 0.012 0.30 k in. mm 0.015 0.38 0.025 0.58
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